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? 2012 microchip technology inc. ds25127a-page 1 mcp6v31/1u features ? high dc precision: -v os drift: 50 nv/c (maximum) -v os : 8 v (maximum) -a ol : 120 db (minimum, v dd =5.5v) - psrr: 120 db (minimum, v dd =5.5v) - cmrr: 120 db (minimum, v dd =5.5v) -e ni : 1.0 v p-p (typical), f = 0.1 hz to 10 hz -e ni : 0.33 v p-p (typical), f = 0.01 hz to 1 hz ? low power and supply voltages: -i q : 23 a/amplifier (typical) - wide supply voltage range: 1.8v to 5.5v ? small packages - singles in sc70, sot-23 ?easy to use: - rail-to-rail input/output - gain bandwidth product: 300 khz (typical) - unity gain stable ? extended temperature range: -40c to +125c typical applications ? portable instrumentation ? sensor conditioning ? temperature measurement ? dc offset correction ? medical instrumentation design aids ? spice macro models ?filterlab ? software ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes related parts ? mcp6v01/2/3: auto-zeroed, spread clock ? mcp6v06/7/8: auto-zeroed ? mcp6v26/7/8: auto-zeroed, low noise ? mcp6v11/1u: zero-drift, low power description the microchip technology inc. mcp6v31/1u family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. these are low power devices, with a gain bandwidth product of 300 khz (typical). they are unity gain stable, have no 1/f noise, and have good power supply rejection ratio (psrr) and common mode rejection ratio (cmrr). these products operate with a single supply voltage as low as 1.8v, while drawing 23 a/amplifier (typical) of quiescent current. the microchip technology inc. mcp6v31/1u op amps are offered in single (mcp6v31 and mcp6v31u) packages. they were designed using an advanced cmos process. package types typical application circuit v in + v ss v in ? 1 2 3 5 4 v dd v out mcp6v31 sot-23 mcp6v31u sc70, sot-23 v in ? v ss v out 1 2 3 5 4 v dd v in + u 1 mcp6xxx offset voltage correction for power driver c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v31 23 a, 300 khz zero-drift op amps
mcp6v31/1u ds25127a-page 2 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 3 mcp6v31/1u 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd ?v ss .............................................................................................................................. ...................................6.5v current at input pins ......................................................................................................... .....................................2 ma analog inputs (v in + and v in ?) ( note 1 ) .....................................................................................v ss ? 1.0v to v dd +1.0v all other inputs and outputs .................................................................................................. .....v ss ? 0.3v to v dd +0.3v difference input voltage ...................................................................................................... ...........................|v dd ?v ss | output short circuit current .................................................................................................. ......................... continuous current at output and supply pins ............................................................................................. ......................... 30 ma storage temperature ........................................................................................................... ..................-65c to +150c maximum junction temperature .................................................................................................. ........................ +150c esd protection on all pins (hbm, cdm, mm) ............................................................... ............................ 2kv,1.5kv,400v note 1: see section 4.2.1, rail-to-rail inputs . 1.2 specifications ?notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3,v out =v dd /2, v l =v dd /2, r l = 100 k ? to v l and c l = 20 pf (refer to figure 1-4 and figure 1-5 ). parameters sym. min. typ. max. units conditions input offset input offset voltage v os -8 ? +8 v t a = +25c input offset voltage drift with temperature (linear temp. co.) tc 1 -50 ? +50 nv/c t a = -40 to +125c ( note 1 ) input offset voltage quadratic te m p . c o . tc 2 ?0.08 ?nv/c 2 t a = -40 to +125c power supply rejection psrr 120 135 ? db input bias current and impedance input bias current i b ?+5 ?pa input bias current across temperature i b ?+20 ?pat a = +85c i b 0+2.9+5nat a = +125c input offset current i os ?130 ?pa input offset current across temperature i os ?140 ?pat a = +85c i os -1 0.4 +1 na t a = +125c common mode input impedance z cm ?10 13 ||6 ? ? ||pf differential input impedance z diff ?10 13 ||6 ? ? ||pf note 1: for design guidance only; not tested. 2: figure 2-18 shows how v cml and v cmh changed across temperature for the first production lot.
mcp6v31/1u ds25127a-page 4 ? 2012 microchip technology inc. common mode common-mode input voltage range low v cml ??v ss ? 0.15 v ( note 2 ) common-mode input voltage range high v cmh v dd +0.2 ? ? v ( note 2 ) common-mode rejection cmrr 110 125 ? db v dd = 1.8v, v cm = -0.15v to 2.0v ( note 2 ) cmrr 120 135 ? db v dd = 5.5v, v cm = -0.15v to 5.7v ( note 2 ) open-loop gain dc open-loop gain (large signal) a ol 103 125 ? db v dd =1.8v, v out = 0.3v to 1.6v a ol 120 135 ? db v dd =5.5v, v out = 0.3v to 5.3v output minimum output voltage swing v ol v ss v ss +14 v ss +45 mv r l =10k ? , g = +2, 0.5v input overdrive v ol ?v ss +1.4 ? mv r l =100k ? , g = +2, 0.5v input overdrive maximum output voltage swing v oh v dd ?45 v dd ?14 v dd mv r l =10k ? , g = +2, 0.5v input overdrive v oh ?v dd ?1.4 ? mv r l =100k ? , g = +2, 0.5v input overdrive output short circuit current i sc ?6 ?mav dd =1.8v i sc ?21 ?mav dd =5.5v power supply supply voltage v dd 1.8 ? 5.5 v quiescent current per amplifier i q 12 23 34 a i o = 0 por trip voltage v por 0.9 ? 1.6 v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3,v out =v dd /2, v l =v dd /2, r l = 100 k ? to v l and c l = 20 pf (refer to figure 1-4 and figure 1-5 ). parameters sym. min. typ. max. units conditions note 1: for design guidance only; not tested. 2: figure 2-18 shows how v cml and v cmh changed across temperature for the first production lot.
? 2012 microchip technology inc. ds25127a-page 5 mcp6v31/1u table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm = v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf (refer to figure 1-4 and figure 1-5 ). parameters sym. min. typ. max. units conditions amplifier ac response gain bandwidth product gbwp ? 300 ? khz slew rate sr ? 0.13 ? v/s phase margin pm ? 70 ? g = +1 amplifier noise response input noise voltage e ni ?0.33?v p-p f = 0.01 hz to 1 hz e ni ?1.0?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?50?nv/ hz f < 2 khz input noise current density i ni ?5?fa/ hz amplifier distortion ( note 1 ) intermodulation distortion (ac) imd ? 52 ? v pk v cm tone = 50 mv pk at 100 hz, g n = 1 amplifier step response start up time t str ? 2 ? ms g = +1, 0.1% v out settling ( note 2 ) offset correction settling time t stl ? 100 ? s g = +1, v in step of 2v, v os within 100 v of its final value output overdrive recovery time t odr ? 120 ? s g = -10, 0.5v input overdrive to v dd /2, v in 50% point to v out 90% point ( note 3 ) note 1: these parameters were characterized using the circuit in figure 1-6 . in figure 2-36 and figure 2-37 , there is an imd tone at dc, a residual tone at 100 hz and other imd tones and clock tones. 2: high gains behave differently; see section 4.3.3, offset at power up . 3: t odr includes some uncertainty due to clock edge timing. table 1-3: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +1.8v to +5.5v, v ss = gnd. parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c ( note 1 ) storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sc-70 ja ?331 ? c/w thermal resistance, 5l-sot-23 ja ?256 ? c/w note 1: operation must not cause t j to exceed maximum junction temperature specification (+150c).
mcp6v31/1u ds25127a-page 6 ? 2012 microchip technology inc. 1.3 timing diagrams figure 1-1: amplifier start up. figure 1-2: offset correction settling time. figure 1-3: output overdrive recovery. 1.4 test circuits the circuits used for most dc and ac tests are shown in figure 1-4 and figure 1-5 . lay the bypass capacitors out as discussed in section 4.3.10, supply bypassing and filtering . r n is equal to the parallel combination of r f and r g to minimize bias current effects. figure 1-4: ac and dc test circuit for most non-inverting gain conditions. figure 1-5: ac and dc test circuit for most inverting gain conditions. the circuit in figure 1-6 tests the input?s dynamic behavior (i.e., imd, t str , t stl and t odr ). the potentiometer balances the resistor network (v out should equal v ref at dc). the op amp?s common mode input voltage is v cm =v in /2. the error at the input (v err ) appears at v out with a noise gain of 10 v/v. figure 1-6: test circuit for dynamic input behavior. v dd v out 1.001(v dd /3) 0.999(v dd /3) t str 0v 1.8v to 5.5v 1.8v v in v os v os +100v v os ?100v t stl v in v out v dd v ss t odr t odr v dd /2 v dd r g r f r n v out v in v dd /3 1f c l r l v l 100 nf r iso mcp6v3x v dd r g r f r n v out v dd /3 v in 1f c l r l v l 100 nf r iso mcp6v3x v dd v out 1f c l v l r iso 11.0 k ? 249 ? 11.0 k ? 500 ? v in v ref =v dd /3 0.1% 0.1% 25 turn 100 k ? 100 k ? 0.1% 0.1% r l 0 ? 20 pf open 100 nf 1% mcp6v3x
? 2012 microchip technology inc. ds25127a-page 7 mcp6v31/1u 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. 2.1 dc input precision figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage quadratic temp. co. figure 2-4: input offset voltage vs. power supply voltage with v cm =v cml . figure 2-5: input offset voltage vs. power supply voltage with v cm =v cmh . figure 2-6: input offset voltage vs. output voltage. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 10% 15% 20% 25% age of occurrences 42 samples t a = +25c v dd = 1.8v and 5.5v 0% 5% -8-7-6-5-4-3-2-1012345678 percent input offset voltage (v) 15% 20% 25% 30% 35% age of occurrences 42 samples v dd = 1.8v and 5.5v 0% 5% 10% -50 -40 -30 -20 -10 0 10 20 30 40 50 percent input offset voltage drift; tc 1 (nv/c) 15% 20% 25% 30% 35% 40% 45% n tage of occurrences 42 samples v dd = 1.8v and 5.5v 0% 5% 10% -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 perce n input offset voltage's quadratic temp co; tc 2 (nv/c 2 ) 6 8 v cm = v cml representative part 4 6 e (v) representative part 0 2 v oltag e -2 0 o ffset v +125c +85 c -4 input o +85 c +25c -40c -8 -6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) 6 8 v cm = v cmh re p resentative part 4 6 e (v) p 0 2 v oltag e -2 0 o ffset v +125c + 85 c -4 input o 85 c +25c -40c -8 -6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) 6 8 representative part 4 6 e (v) 0 2 v oltag e v dd = 1.8v -2 0 o ffset v v dd = 5.5v -4 i nput o - 8 -6 i 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v)
mcp6v31/1u ds25127a-page 8 ? 2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. figure 2-7: input offset voltage vs. common mode voltage with v dd =1.8v. figure 2-8: input offset voltage vs. common mode voltage with v dd =5.5v. figure 2-9: cmrr. figure 2-10: psrr. figure 2-11: dc open-loop gain. figure 2-12: cmrr and psrr vs. ambient temperature. 6 8 v dd = 1.8v representative part 4 6 e (v) representative part 0 2 v oltag e -2 0 o ffset v -4 input o +125c +85c +25 c -8 -6 +25 c -40c -0.5 0.0 0.5 1.0 1.5 2.0 2.5 input common mode voltage (v) 6 8 v dd = 5.5v representative part 4 6 e (v) representative part 0 2 v oltag e -2 0 o ffset v -4 input o +125c +85c +25 c -8 -6 +25 c -40c -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input common mode voltage (v) 30% 40% 50% 60% 70% 80% tage of occurrences 21 samples t a = 25c v dd = 5.5v 0% 10% 20% -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 percen 1/cmrr (v/v) v dd = 1.8v 45% 50% s 20 samples t a = +25c 35% 40% r rence s 25% 30% 35% occu r 20% 25% a ge of 10% 15% e rcent a 0% 5% p e -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1/psrr (v/v) 80% 90% s 21 samples t a = +25c 60% 70% r rence s 50% 60% occu r v dd = 5.5v 30% 40% a ge of 20% 30% e rcent a v dd = 1.8v 0% 10% p e v dd 1.8v -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 1/a ol (v/v) 155 160 145 150 b) psrr 135 140 145 s rr (d 130 135 rr, p s 120 125 cm cmrr v =55v 110 115 cmrr v dd =5 . 5v v dd = 1.8v -50 -25 0 25 50 75 100 125 ambient temperature (c)
? 2012 microchip technology inc. ds25127a-page 9 mcp6v31/1u note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. figure 2-13: dc open-loop gain vs. ambient temperature. figure 2-14: input bias and offset currents vs. common mode input voltage with t a = +85c. figure 2-15: input bias and offset currents vs. common mode input voltage with t a = +125c. figure 2-16: input bias and offset currents vs. ambient temperature with v dd =+5.5v. figure 2-17: input bias current vs. input voltage (below v ss ). 155 160 145 150 n (db) v dd = 5.5v 135 140 145 o p gai n v dd = 1.8v 130 135 e n-lo o 120 125 d c op e 110 115 d -50 -25 0 25 50 75 100 125 ambient temperature (c) 150 200 p a) t a = +85c v dd = 5.5v 100 150 ents ( p dd 0 50 e t curr i b -50 0 s , offs e -100 u t bia s i os -200 -150 inp u i os -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) 4000 5000 p a) t a = +125c v =55v 3000 4000 r ents ( p v dd =5 . 5v 2000 e t cur r i 1000 s , offs e i b 1000 0 u t bia s i os -2000 - 1000 inp u -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) 10000 a ) v dd = 5.5v 1n 1000 r ents ( a 1n 100 e t cur r i os 100 100 s , offs e 100 p 10 ut bia s i b 10p 1 inp 1p 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) 1p 1.e - 03 1.e-02 a ) 10m 1m 1.e-04 1.e 03 ude ( a 1m 100 1.e-06 1.e-05 m agnit 10 1 1e - 08 1.e-07 u rrent m +125c +85 c 100n 10n 1.e-09 1 . e - 08 put c u +85 c +25c -40c 10n 1n 1.e-11 1.e-10 in 100p 10 p -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) p
mcp6v31/1u ds25127a-page 10 ? 2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. 2.2 other dc voltages and currents figure 2-18: input common mode voltage headroom (range) vs. ambient temperature. figure 2-19: output voltage headroom vs. output current. figure 2-20: output voltage headroom vs. ambient temperature. figure 2-21: output short circuit current vs. power supply voltage. figure 2-22: supply current vs. power supply voltage. figure 2-23: power-on reset trip voltage. 03 0.4 g e 1 wafer lot 0.2 0 . 3 volta g upper ( v cmh Cv dd ) 00 0.1 mode o m (v) -0.1 0 . 0 m mon h eadro o -0.2 p ut co m h lower (v cml Cv ss ) -0.4 -0.3 in p -50 -25 0 25 50 75 100 125 ambient temperature (c) 1000 v ) r oom ( v v dd C v oh 100 head r v dd v oh v dd = 5.5v v ol Cv ss 10 v oltage v dd = 1.8 v 10 u tput v 1 o u 0.1 1 10 output current magnitude (v) 4 5 6 7 8 9 10 11 12 u t headroom (mv) v dd Cv oh v dd = 5.5v v ol Cv ss r l = 25 k 0 1 2 3 4 -50 -25 0 25 50 75 100 125 outp u ambient temperature (c) v dd = 1.8v -10 0 10 20 30 40 o rt circuit current (ma) -40c +25c +85c +125c -40 -30 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 output sh o power supply voltage (v) +125c +85c +25c -40c 10 15 20 25 30 c urrent (a/amplifier) +125c +85c 0 5 10 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply c power supply voltage (v) +25c -40c 35% 40% e s 850 samples 1 wafer lot 30% 35% rrenc e 1 wafer lot t a = +25c 20% 25% f occu 15% 20% t age o f 5% 10% p ercen t 0% 5% 0 2 4 6 8 0 2 4 6 8 0 p 1.1 0 1.1 2 1.1 4 1.1 6 1.1 8 1.2 0 1.2 2 1.2 4 1.2 6 1.2 8 1.3 0 por trip voltage (v)
? 2012 microchip technology inc. ds25127a-page 11 mcp6v31/1u note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. figure 2-24: power-on reset voltage vs. ambient temperature. 0.6 0.8 1.0 1.2 1.4 1.6 r trip voltage (v) 0.0 0.2 0.4 -50 -25 0 25 50 75 100 125 po r ambient temperature (c)
mcp6v31/1u ds25127a-page 12 ? 2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. 2.3 frequency response figure 2-25: cmrr and psrr vs. frequency. figure 2-26: open-loop gain vs. frequency with v dd =1.8v. figure 2-27: open-loop gain vs. frequency with v dd =5.5v. figure 2-28: gain bandwidth product and phase margin vs. ambient temperature. figure 2-29: gain bandwidth product and phase margin vs. common mode input voltage. figure 2-30: gain bandwidth product and phase margin vs. output voltage. 50 60 70 80 90 100 110 r r, psrr (db) cmrr 10 20 30 40 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 cm r frequency (hz) cmrr psrr 10 10k 100 100k 1k 180 -150 -120 -90 -60 -30 0 10 20 30 40 50 60 70 n -loop phase () n -loop gain (db) a ol v dd = 1.8v c l = 20 pf -270 -240 -210 - 180 -20 -10 0 10 1.e+03 1.e+04 1.e+05 1.e+06 ope n ope n frequency (hz) 1k 10k 1m 100k | a ol | 180 -150 -120 -90 -60 -30 0 10 20 30 40 50 60 70 n -loop phase () n -loop gain (db) | a o l | a ol v dd = 5.5v c l = 20 pf -270 -240 -210 - 180 -20 -10 0 10 1.e+03 1.e+04 1.e+05 1.e+06 ope n ope n frequency (hz) 1k 10k 1m 100k 60 70 80 90 100 300 400 500 600 700 h ase margin () d width product (khz) v dd = 5.5v pm 30 40 50 0 100 200 -50 -25 0 25 50 75 100 125 p h gain ban d ambient temperature (c) gbwp v dd = 1.8v 60 70 80 90 100 300 400 500 600 700 h ase margin () dwidth product (khz) v dd = 5.5v pm r f = 1 m 30 40 50 0 100 200 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 p h gain ban common mode input voltage (v) gbwp v dd = 1.8v 60 70 80 90 100 300 400 500 600 700 h ase margin () dwidth product (khz) v dd = 5.5v pm 30 40 50 0 100 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 p h gain ban output voltage (v) gbwp v dd = 1.8v
? 2012 microchip technology inc. ds25127a-page 13 mcp6v31/1u note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. figure 2-31: closed-loop output impedance vs. frequency with v dd =1.8v. figure 2-32: closed-loop output impedance vs. frequency with v dd =5.5v. figure 2-33: maximum output voltage swing vs. frequency. 1.e+02 1.e+03 1.e+04 1.e+05 o p output impedance () 100 1k 10k 100k v dd = 1.8v 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 closed-lo o frequency (hz) 100 1k 10k 1m 1 g = 1 v/v g = 11 v/v g = 101 v/v 10 100k 1.e+02 1.e+03 1.e+04 1.e+05 o p output impedance () 100 1k 10k 100k v dd = 5.5v 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 closed-lo o frequency (hz) 100 1k 100k 1m 10 g = 1 v/v g = 11 v/v g = 101 v/v 10 10k 10 i ng g e sw i v dd = 5.5v 1 t volta g - p ) v dd = 1.8v 1 outpu t (v p - x imum 01 ma x 0 . 1 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) 1k 10k 1m 100k
mcp6v31/1u ds25127a-page 14 ? 2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. 2.4 input noise and distortion figure 2-34: input noise voltage density and integrated input noise voltage vs. frequency. figure 2-35: input noise voltage density vs. input common mode voltage. figure 2-36: inter-modulation distortion vs. frequency with v cm disturbance (see figure 1-6 ). figure 2-37: inter-modulation distortion vs. frequency with v dd disturbance (see figure 1-6 ). figure 2-38: input noise vs. time with 1 hz and 10 hz filters and v dd =1.8v. figure 2-39: input noise vs. time with 1 hz and 10 hz filters and v dd =5.5v. 10 100 1000 10 100 1000 d input noise voltage; e ni (v p-p ) o ise voltage density; e ni (nv/ hz) e ni 1 10 1 10 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 integrate d input no frequency (hz) e ni (0 hz to f) v dd = 5.5v v dd = 1.8v 1 10 100 1k 10k 100k 70 80 y f < 2 khz 60 70 d ensit y v dd = 1.8v 40 50 o ltage d hz) 30 40 o ise v o (nv/ v dd = 5.5v 10 20 n put n o 0 10 i n -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) 1000 g dm = 1 v/v v cm tone = 50 mv pk , f = 100 hz 100 ( v pk ) cm pk 10 m , rti ( 10 p ectru m residual 100 hz tone 1 md s p 01 i v dd = 1.8v v dd = 5.5v 0 . 1 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) 1 100 100k 10k 10 1k 1000 g dm = 1 v/v v dd tone = 50 mv pk , f = 100 hz 100 ( v pk ) 10 m , rti ( imd tone at dc 10 p ectru m 100 hz tone 1 md s p v dd = 1.8v v 55v 01 i v dd = 5 . 5v 0 . 1 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 frequency (hz) 1 100 100k 10k 10 1k n oise voltage; e ni (t) (0.2 v/div) v dd = 1.8v 0 102030405060708090100 input n time (s) npbw = 10 hz npbw = 1 hz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 n oise voltage; e ni (t) (0.2 v/div) v dd = 5.5v -0.8 -0.6 -0.4 -0.2 0 102030405060708090100 input n time (s) npbw = 10 hz npbw = 1 hz
? 2012 microchip technology inc. ds25127a-page 15 mcp6v31/1u note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. 2.5 time response figure 2-40: input offset voltage vs. time with temperature change. figure 2-41: input offset voltage vs. time at power up. figure 2-42: the mcp6v31/1u family shows no input phase reversal with overdrive. figure 2-43: non-inverting small signal step response. figure 2-44: non-inverting large signal step response. figure 2-45: inverting small signal step response. 60 80 35 40 20 40 25 30 (c) e (v) t pcb 20 0 20 15 20 25 e rature v oltag e v dd = 1.8v v dd = 5.5v -40 - 20 10 15 t emp e o ffset v v os v dd 5.5v -80 -60 0 5 pcb t i nput o v os -120 -100 -10 -5 i temperature increased by using heat gun for 5 seconds. 0 102030405060708090100 time (s) 0 1 2 3 4 5 6 0 1 2 3 4 5 6 supply voltage (v) o ffset voltage (mv) por trip point v os v dd g = 1 -4 -3 -2 -1 -4 -3 -2 -1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 power input o time (ms) v os 2 3 4 5 6 7 o utput voltage (v) v dd = 5.5v g = 1 v out v in -1 0 1 012345678910 input, o time (ms) 30 40 50 60 70 80 v oltage (10 mv/div) v dd = 5.5v g = 1 0 10 20 0 102030405060708090100 output v time (s) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t put voltage (v) v dd = 5.5v g = 1 0.0 0.5 1.0 1.5 0 50 100 150 200 250 300 350 400 ou t time (s) 30 40 50 60 70 80 90 v oltage (10 mv/div) v dd = 5.5v g = -1 -10 0 10 20 0 102030405060708090100 output v time (s)
mcp6v31/1u ds25127a-page 16 ? 2012 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =100k ? to v l and c l = 20 pf. figure 2-46: inverting large signal step response. figure 2-47: slew rate vs. ambient temperature. figure 2-48: output overdrive recovery vs. time with g = -10 v/v. figure 2-49: output overdrive recovery time vs. inverting gain. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t put voltage (v) v dd = 5.5v g = -1 0.0 0.5 1.0 1.5 0 50 100 150 200 250 300 350 400 ou t time (s) 010 0.15 0.20 0.25 0.30 e w rate (v/s) falling edge v dd = 5.5v 0.00 0.05 0 . 10 -50 -25 0 25 50 75 100 125 sl e ambient temperature (c) v dd = 1.8v rising edge 2 3 4 5 6 7 2 3 4 5 6 7 ltage g (1 v/div) p ut voltage (v) v =55v v out g v in -1 0 1 2 -1 0 1 2 0 100 200 300 400 500 600 700 800 900 10001100 input vo out p time (100 s/div) v dd =5 . 5v g = -10 v/v 0.5v overdrive v out g v in 1e 04 1.e-03 1.e-02 v e recovery time (s) 0.5v input overdrive t odr , high v dd = 5.5v v dd = 1.8v 10m 1m 100 1.e-05 1 . e - 04 1 10 100 1000 overdri v inverting gain magnitude (v/v) t odr , low 100 10
? 2012 microchip technology inc. ds25127a-page 17 mcp6v31/1u 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in ?, ?) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 1.8v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. mcp6v31 mcp6v31u symbol description sot-23 sot-23, sc-70 14v out output (op amp a) 22v ss negative power supply 31v in + non-inverting input (op amp a) 43v in ? inverting input (op amp a) 55v dd positive power supply
mcp6v31/1u ds25127a-page 18 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 19 mcp6v31/1u 4.0 applications the mcp6v31/1u family of zero-drift op amps is manufactured using microchip?s state of the art cmos process. it is designed for precision applications with requirements for small packages and low power. its low supply voltage and low quiescent current make the mcp6v31/1u devices ideal for battery-powered applications. 4.1 overview of zero-drift operation figure 4-1 shows a simplified diagram of the mcp6v31/1u zero-drift op amps. this diagram will be used to explain how slow voltage errors are reduced in this architecture (much better v os , ? v os / ? t a (tc 1 ), cmrr, psrr, a ol and 1/f noise). figure 4-1: simplified zero-drift op amp functional diagram. 4.1.1 building blocks the main amplifier is designed for high gain and bandwidth, with a differential topology. its main input pair (+ and - pins at the top left) is used for the higher frequency portion of the input signal. its auxiliary input pair (+ and - pins at the bottom left) is used for the low frequency portion of the input signal and corrects the op amp?s input offset voltage. both inputs are added together internally. the auxiliary amplifier, chopper input switches and chopper output switches provide a high dc gain to the input signal. dc errors are modulated to higher frequencies, while white noise is modulated to low frequency. the low-pass filter reduces high frequency content, including harmonics of the chopping clock. the output buffer drives external loads at the v out pin (v ref is an internal reference voltage). the oscillator runs at f osc1 = 200 khz. its output is divided by two, to produce the chopping clock rate of f chop =100khz. the internal por part starts the part in a known good state, protecting against power supply brown-outs. the digital control block controls switching and por events. 4.1.2 chopping action figure 4-2 shows the amplifier connections for the first phase of the chopping clock and figure 4-3 shows them for the second phase. its slow voltage errors alternate in polarity, making the average error small. figure 4-2: first chopping clock phase; equivalent amplifier diagram. figure 4-3: second chopping clock phase; equivalent amplifier diagram. v in + v in ? main buffer v out v ref amp. output nc aux. amp. chopper input switches chopper output switches oscillator low-pass filter por digital control v in + v in ? main amp. nc aux. amp. low-pass filter v in + v in ? main amp. nc aux. amp. low-pass filter
mcp6v31/1u ds25127a-page 20 ? 2012 microchip technology inc. 4.1.3 intermodulation distortion (imd) these op amps will show intermodulation distortion (imd) products when an ac signal is present. the signal and clock can be decomposed into sine wave tones (fourier series components). these tones interact with the zero-drift circuitry?s non-linear response to produce imd tones at sum and difference frequencies. each of the square wave clock?s harmonics has a series of imd tones centered on it. see figure 2-36 and figure 2-37 . 4.2 other functional blocks 4.2.1 rail-to-rail inputs the input stage of the mcp6v31/1u op amps uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm , which is approximately equal to v in + and v in ? in normal operation) and the other at high v cm . with this topology, the input operates with v cm up to v dd +0.2v, and down to v ss ? 0.15v, at +25c (see figure 2-18 ). the input offset voltage (v os ) is measured at v cm =v ss ? 0.15v and v dd + 0.2v to ensure proper operation. the transition between the input stages occurs when v cm v dd ?0.9v (see figure 2-7 and figure 2-8 ). for the best distortion and gain linearity, with non-inverting gains, avoid this region of operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-42 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 input voltage limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see section 1.1, absolute maximum ratings ? ). this requirement is independent of the cur- rent limits discussed later on. the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors against many (but not all) overvoltage conditions, and to minimize input bias current (i b ). figure 4-4: simplified analog input esd structures. the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that well above v dd ; their breakdown voltage is high enough to allow normal operation, but not low enough to protect against slow overvoltage (beyond v dd ) events. very fast esd events (that meet the spec) are limited so that damage does not occur. in some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; figure 4-5 shows one approach to protecting these inputs. d 1 and d 2 may be small signal silicon diodes, schottky diodes for lower clamping voltages or diode connected fets for low leakage. figure 4-5: protecting the analog inputs against high voltages. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in ? v 1 v dd d 1 v out v 2 d 2 u 1 mcp6v3x
? 2012 microchip technology inc. ds25127a-page 21 mcp6v31/1u 4.2.1.3 input current limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see section 1.1, absolute maximum ratings ? ). this requirement is independent of the volt- age limits discussed previously. figure 4-6 shows one approach to protecting these inputs. the resistors r 1 and r 2 limit the possible current in or out of the input pins (and into d 1 and d 2 ). the diode currents will dump onto v dd . figure 4-6: protecting the analog inputs against high currents. it is also possible to connect the diodes to the left of resistors r 1 and r 2 . in this case, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in ?) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-17 . 4.2.2 rail-to-rail output the output voltage range of the mcp6v31/1u zero-drift op amps is v dd ?20mv (minimum) and v ss +20mv (maximum) when r l =10k ? is connected to v dd /2 and v dd = 5.5v. refer to figure 2-19 and figure 2-20 for more information. this op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.3 application tips 4.3.1 input offset voltage over temperature table 1-1 gives both the linear and quadratic temperature coefficients (tc 1 and tc 2 ) of input offset voltage. the input offset voltage, at any temperature in the specified range, can be calculated as follows: equation 4-1: 4.3.2 dc gain plots figures 2-9 to 2-11 are histograms of the reciprocals (in units of v/v) of cmrr, psrr and a ol , respectively. they represent the change in input offset voltage (v os ) with a change in common mode input voltage (v cm ), power supply voltage (v dd ) and output voltage (v out ). the 1/a ol histogram is centered near 0 v/v because the measurements are dominated by the op amp?s input noise. the negative values shown represent noise and tester limitations, not unstable behavior. production tests make multiple v os measurements, which validates an op amp's stability; an unstable part would show greater v os variability, or the output would stick at one of the supply rails. 4.3.3 offset at power up when these parts power up, the input offset (v os ) starts at its uncorrected value (usually less than 5 mv). circuits with high dc gain can cause the output to reach one of the two rails. in this case, the time to a valid output is delayed by an output overdrive time (like t odr ), in addition to the startup time (like t str ). it can be simple to avoid this extra startup time. reducing the gain is one method. adding a capacitor across the feedback resistor (r f ) is another method. v 1 r 1 v dd d 1 min(r 1 ,r 2 )> v ss ?min(v 1 ,v 2 ) 2ma v out v 2 r 2 d 2 min(r 1 ,r 2 )> max(v 1 ,v 2 )?v dd 2ma u 1 mcp6v3x v os t a () v os tc 1 ttc 2 t 2 ++ = where: ? t=t a ?25c v os (t a ) = input offset voltage at t a v os = input offset voltage at +25c tc 1 = linear temperature coefficient tc 2 = quadratic temperature coefficient
mcp6v31/1u ds25127a-page 22 ? 2012 microchip technology inc. 4.3.4 source resistances the input bias currents have two significant components; switching glitches that dominate at room temperature and below, and input esd diode leakage currents that dominate at +85c and above. make the resistances seen by the inputs small and equal. this minimizes the output offset caused by the input bias currents. the inputs should see a resistance on the order of 10 ? to 1 k ? at high frequencies (i.e., above 1 mhz). this helps minimize the impact of switching glitches, which are very fast, on overall performance. in some cases, it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. small input resistances may be needed for high gains. without them, parasitic capacitances might cause positive feedback and instability. 4.3.5 source capacitance the capacitances seen by the two inputs should be small and matched. the internal switches connected to the inputs dump charges on these capacitors; an offset can be created if the capacitances do not match. large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. 4.3.6 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. these zero-drift op amps have a different output impedance than most op amps, due to their unique topology. when driving a capacitive load with these op amps, a series resistor at the output (r iso in figure 4-7 ) improves the feedback loop?s phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-7: output resistor, r iso , stabilizes capacitive loads. figure 4-8 gives recommended r iso values for different capacitive loads and gains. the x-axis is the load capacitance (c l ). the y-axis is the resistance (r iso ). g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n = +2 v/v). figure 4-8: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation is helpful. 4.3.7 stabilizing output loads this family of zero-drift op amps has an output impedance ( figure 2-31 and figure 2-32 ) that has a double zero when the gain is low. this can cause a large phase shift in feedback networks that have low impedance near the part?s bandwidth. this large phase shift can cause stability problems. figure 4-9 shows that the load on the output is (r l +r iso )||(r f +r g ), where r iso is before the load (like figure 4-7 ). this load needs to be large enough to maintain performance; it should be at least 10 k ? . figure 4-9: output load. r iso c l v out u 1 mcp6v3x 1.e+03 1.e+04 m mended r iso () r l ||(r f + r g ) 100 k 10k 1k 1.e+02 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 reco m capacitive load (f) g n = 1 g n = 10 g n = 100 100 10p 100p 1n 10n 100n 1 r g r f v out u 1 mcp6v3x r l c l
? 2012 microchip technology inc. ds25127a-page 23 mcp6v31/1u 4.3.8 gain peaking figure 4-10 shows an op amp circuit that represents non-inverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the capacitances c n and c g rep- resent the total capacitance at the input pins; they include the op amp?s common mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. the capacitance c fp represents the parasitic capacitance coupling the output and non- inverting input pins. figure 4-10: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by either reducing c g or r f ||r g . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 r n c n ). the largest value of r f that should be used depends on noise gain (see g n in section 4.3.6, capacitive loads ), c g and the open-loop gain?s phase shift. an approximate limit for r f is: equation 4-2: some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). at high gains, r n needs to be small, in order to prevent positive feedback and oscillations. large c n values can also help. 4.3.9 reducing undesired noise and signals reduce undesired noise and signals with: ? low bandwidth signal filters: - minimizes random analog noise - reduces interfering signals ? good pcb layout techniques: - minimizes crosstalk - minimizes parasitic capacitances and inductances that interact with fast switching edges ? good power supply design: - isolation from other parts - filtering of interference on supply line(s) 4.3.10 supply bypassing and filtering with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm of the pin for good high-frequency performance. these parts also need a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other low noise, analog parts. in some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion, with a dc offset shift; this noise needs to be filtered. adding a resistor into the supply connection can be helpful. 4.3.11 pcb design for dc precision in order to achieve dc precision on the order of 1 v, many physical errors need to be minimized. the design of the printed circuit board (pcb), the wiring, and the thermal environment have a strong impact on the precision achieved. a poor pcb design can easily be more than 100 times worse than the mcp6v31/1u op amps? minimum and maximum specifications. 4.3.11.1 pcb layout any time two dissimilar metals are joined together, a temperature dependent voltage appears across the junction (the seebeck or thermojunction effect). this effect is used in thermocouples to measure temperature. the following are examples of thermojunctions on a pcb: ? components (resistors, op amps, ?) soldered to a copper pad ? wires mechanically attached to the pcb ? jumpers ? solder joints ?pcb vias r g r f v out u 1 mcp6v3x c g r n c n v m v p c fp r f 10 k () 12 pf c g ------------- - g n 2
mcp6v31/1u ds25127a-page 24 ? 2012 microchip technology inc. typical thermojunctions have temperature to voltage conversion coefficients of 1 to 100 v/c (sometimes higher). microchip?s an1258 (? op amp precision design: pcb layout techniques ?) contains in-depth information on pcb layout techniques that minimize thermojunction effects. it also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. 4.3.11.2 crosstalk dc crosstalk causes offsets that appear as a larger input offset voltage. common causes include: ? common mode noise (remote sensors) ? ground loops (current return paths) ? power supply coupling interference from the mains (usually 50 hz or 60 hz), and other ac sources, can also affect the dc performance. non-linear distortion can convert these signals to multiple tones, including a dc shift in voltage. when the signal is sampled by an adc, these ac signals can also be aliased to dc, causing an apparent shift in offset. to reduce interference: - keep traces and wires as short as possible - use shielding - use ground plane (at least a star ground) - place the input signal source near to the dut - use good pcb layout techniques - use a separate power supply filter (bypass capacitors) for these zero-drift op amps 4.3.11.3 miscellaneous effects keep the resistances seen by the input pins as small and as near to equal as possible, to minimize bias- current-related offsets. make the (trace) capacitances seen by the input pins small and equal. this is helpful in minimizing switching glitch-induced offset voltages. bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the triboelectric effect). make sure the bending radius is large enough to keep the conductors and insulation in full contact. mechanical stresses can make some capacitor types (such as some ceramics) to output small voltages. use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. humidity can cause electrochemical potential voltages to appear in a circuit. proper pcb cleaning helps, as does the use of encapsulants. 4.4 typical applications 4.4.1 wheatstone bridge many sensors are configured as wheatstone bridges. strain gauges and pressure sensors are two common examples. these signals can be small and the common mode noise large. amplifier designs with high differential gain are desirable. figure 4-11 shows how to interface to a wheatstone bridge with a minimum of components. because the circuit is not symmetric, the adc input is single ended, and there is a minimum of filtering, the cmrr is good enough for moderate common mode noise. figure 4-11: simple design. 4.4.2 rtd sensor the ratiometric circuit in figure 4-12 conditions a two- wire rtd, for applications with a limited temperature range. u 1 acts a difference amplifier, with a low frequency pole. the sensor?s wiring resistance (r w ) is corrected in firmware. failure (open) of the rtd is detected by an out-of-range voltage. figure 4-12: rtd sensor. v dd rr rr 100r 0.01c adc v dd 0.2r 0.2r 1k ? u 1 mcp6v31 r f 10 nf adc v dd r n 1.0 f v dd r w r t r b r rtd r g 100 ? 1.00 k ? 4.99 k ? 34.8 k ? 2.00 m ? 10.0 k ? u 1 mcp6v31 r w 10.0 k ? r f 2.00 m ? 10 nf 100 nf
? 2012 microchip technology inc. ds25127a-page 25 mcp6v31/1u 4.4.3 offset voltage correction figure 4-13 shows mcp6v31 (u 2 ) correcting the input offset voltage of another op amp (u 1 ). r 2 and c 2 integrate the offset error seen at u 1 ?s input; the integration needs to be slow enough to be stable (with the feedback provided by r 1 and r 3 ). r 4 and r 5 attenuate the integrator?s output; this shifts the integrator pole down in frequency. figure 4-13: offset correction. 4.4.4 precision comparator use high gain before a comparator to improve the latter?s performance. do not use mcp6v31/1u as a comparator by itself; the v os correction circuitry does not operate properly without a feedback loop. figure 4-14: precision comparator. u 1 mcp6xxx c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v31 v in r 3 r 2 v dd /2 v out r 5 r 4 r 1 u 1 mcp6v31 u 2 mcp6541
mcp6v31/1u ds25127a-page 26 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 27 mcp6v31/1u 5.0 design aids microchip provides the basic design aids needed for the mcp6v31/1u family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6v31/1u op amps is available on the microchip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the op amp?s linear region of operation over the temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filterlab ? design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design require- ment. available at no cost from the microchip web site at www.microchip.com/maps , maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demon- stration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their correspond- ing user?s guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: ? mcp6v01 thermocouple auto-zeroed reference design (p/n mcp6v01rd-tcpl) ? mcp6xxx amplifier evaluation board 1 (p/n ds51667) ? mcp6xxx amplifier evaluation board 2 (p/n ds51668) ? mcp6xxx amplifier evaluation board 3 (p/n ds51673) ? mcp6xxx amplifier evaluation board 4 (p/n ds51681) ? active filter demo board kit (p/n ds51614) ? 8-pin soic/msop/tssop/dip evaluation board (p/n soic8ev) ? 14-pin soic/tssop/dip evaluation board (p/n soic14ev) 5.5 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. adn003: ?select the right operational amplifier for your filtering circuits? , ds21821 an722: ?operational amplifier topologies and dc specifications? , ds00722 an723: ?operational amplifier ac specifications and applications? , ds00723 an884: ?driving capacitive loads with op amps? , ds00884 an990: ?analog sensor conditioning circuits ? an overview? , ds00990 an1177: ?op amp precision design: dc errors? , ds01177 an1228: ?op amp precision design: random noise ?, ds01228 an1258: ?op amp precision design: pcb layout techniques? , ds01258 these application notes and others are listed in the design guide: ?signal chain design guide?, ds21825
mcp6v31/1u ds25127a-page 28 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 29 mcp6v31/1u 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 5-lead sc70 ( mcp6v31u ) example : device code mcp6v31ut-e/lt dknn note: applies to 5-lead sc-70. 5-lead sot-23 (mcp6v31, mcp6v31u) example : device code mcp6v31t-e/ot 2bnn mcp6v31ut-e/ot 2enn note: applies to 5-lead sot-23. 2b25 dk25
mcp6v31/1u ds25127a-page 30 ? 2012 microchip technology inc.

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? 2012 microchip technology inc. ds25127a-page 33 mcp6v31/1u note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp6v31/1u ds25127a-page 34 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 35 mcp6v31/1u appendix a: revision history revision a (march 2012) ? original release of this document.
mcp6v31/1u ds25127a-page 36 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 37 mcp6v31/1u product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6v31t single op amp (tape and reel) (sot-23) mcp6v31ut single op amp (tape and reel) (sc-70, sot-23) temperature range: e = -40c to +125c package: lt = plastic package (sc-70), 5-lead ot = plastic small outline transistor (sot-23), 5-lead part no. ?x /xx package temperature range device examples: a) mcp6v31t-e/ot: tape and reel, extended temperature, 5ld sot-23 package a) mcp6v31ut-e/lt: tape and reel extended temperature, 5ld sc70 package b) mcp6v31ut-e/ot: tape and reel, extended temperature, 5ld sot-23 package t tape and reel
mcp6v31/1u ds25127a-page 38 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25127a-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-162076-154-0 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management system certified by dnv == iso/ts 16949 ==
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